In recent years, there has been a noticeable increase in capacity of non-volatile semiconductor storage devices typified by flash memories, going as far as the release of products having a capacity of several hundred gigabytes being announced. The product value of the non-volatile semiconductor storage device is increasing, in particular as storage for USB memories and mobile telephones. Also, the non-volatile semiconductor storage device utilizes the fundamental advantages peculiar to a solid state memory—vibration resistance, high reliability, and low power consumption—and is becoming mainstream as a storage device for mobile type or portable type electronic instruments for music and images.
Meanwhile, apart from the heretofore described storage-oriented application, research is being vigorously carried out aimed at, by giving non-volatility to a DRAM currently being used as a main memory of an information instrument, realizing a computer, a so-called “instant-on computer”, that starts up instantly when used and whose power consumption is unrestrictedly zero when waiting. In order to realize this, a memory that satisfies requirements of (1) a switching speed less than 50 ns and (2) a rewrite quantity exceeding 1016 which are technical specifications required as a DRAM, and that includes non-volatility, is said to be appropriate.
As candidates for this kind of next generation non-volatile semiconductor storage device, research and development is being carried out on non-volatile memory elements based on various kinds of principle, such as a ferroelectric memory (FeRAM), a magnetic memory (MRAM), and a phase-change memory (PRAM). Even among these kinds of non-volatile memory, the MRAM is seen as being promising as a candidate that satisfies the heretofore described technical specifications for replacing the DRAM. The rewrite quantity (>1016) cited in the heretofore described technical specifications is a figure assumed based on an access quantity when continuing to access at 30 ns for 10 years. However, as no refresh cycle is appropriate when the memory is non-volatile, it may be that such a large quantity is not appropriate. The MRAM is at the prototype level but, as it has achieved a rewrite quantity of 1012 or more and the switching speed thereof is high (<10 ns), feasibility is seen as being particularly high in comparison with technologies forming other candidates as a non-volatile semiconductor storage device.
Problems with the MRAM are that the cell area is large and that the write energy is large. As the currently commercialized small capacity (in the region of 4 Mbit) MRAM is a current produced magnetic field rewrite type, the cell area thereof is far too large at 20 to 30 F2 (F is the minimum processing dimension in the manufacturing process) or more, because of which, it is not practical as DRAM replacement means. In response to this, two breakthrough technologies are in the process of changing the situation. One is an MTJ (magnetic tunnel junction) using an MgO tunnel insulation film, and according to the MTJ, a magnetoresistance of 200% or more is easily obtained (for example, refer to Non-patent Document 1). The other is a spin torque transfer method (hereafter abbreviated to STT method). According to the STT method, as it is possible to avoid an increase of reversed magnetic fields in minute cells, which is fatal with the current produced magnetic field rewrite method, it is possible to reduce write energy due to scaling. According to the STT method, as one transistor to one MTJ is ideally possible, it is assumed that the cell area is equivalent to that of the DRAM (6 to 8 F2) (for example, refer to Patent Document 1, Non-patent Document 2).
Herein, a simple description will be given, using FIG. 11, of an action of the heretofore described heretofore known MRAM. FIG. 11 is an enlarged sectional view of a storage device 10′ showing a portion including a magnetoresistance element 1′. The storage device 10′ shown in FIG. 11 carries out an action equivalent to that described in Patent Document 1.
The magnetoresistance element 1′ has a magnetic tunnel junction (MTJ) portion 13, and is configured in such away that the MTJ portion 13 is sandwiched by a lower electrode 14 and an upper electrode 12. The MTJ portion 13 is of a structure wherein a pinned layer 22 (a first magnetic body), an insulation layer 21, a storage layer 20 (a second magnetic body), and the upper electrode 12 are stacked sequentially from below (the lower electrode 14 side). The pinned layer 22 and storage layer 20 are formed of perpendicularly magnetized films. The lower electrode 14 is disposed on a drain region 24 formed in a silicon substrate 15, and furthermore, a source region 25 is formed in the silicon substrate 15 at a distance from the drain region 24. Agate line 16 is formed in a portion above the drain region 24 and source region 25, isolated from them, and a MOS-FET is configured of the drain region 24, source region 25, and gate line 16. Furthermore, a contact portion 17 and a word portion 18 are stacked sequentially on the source region 25, and the word line 18 is connected to an unshown control circuit. Also, the upper electrode 12 is connected to a bit line 11, and the bit line 11 is also connected to the unshown control circuit. The bit line 11 and word line 18 are isolated from each other by an interlayer insulation film 23.
Next, a description will be given, using FIG. 12, of an operating principle of the heretofore known magnetoresistance element 1′. FIG. 12 is an enlarged view of the MTJ portion 13 in FIG. 11.
In the magnetoresistance element 1′ configured as in FIG. 12, the resistance value changes in accordance with a relative magnetization direction of the storage layer 20 with respect to the pinned layer 22 (a TMR effect). Specifically, when the magnetization direction of the storage layer 20 is a direction opposite to that of the pinned layer 22 (the condition of FIG. 12(a)), the insulation layer 21 is in a high resistance condition, while when the magnetization direction of the storage layer 20 is the same direction as that of the pinned layer 22 (the condition of FIG. 12(b)), the insulation layer 21 is in a low resistance condition. Utilizing this, a high resistance condition is caused to correspond to “0” and a low resistance condition to “1”, and the magnetization condition (data) of the storage layer 20 is read as a resistance value. This is the read principle.
With regard to a write, by causing a current 103 oriented from the storage layer 20 toward the pinned layer 22 to flow, as in FIG. 12, the storage layer 20 changes from a high resistance condition to a low resistance condition. Also, by causing an oppositely oriented current to flow through the storage layer 20 when it is in a low resistance condition, the layer 20 changes from a low resistance condition to a high resistance condition. This is the write principle (refer to Non-patent Document 2). In the way heretofore described, the storage device 10′ selects the magnetoresistance element 1′ using a corresponding MOS-FET, reads information stored in the magnetoresistance element 1′, and writes information into the magnetoresistance element 1′.
Meanwhile, there is also a proposal for one diode to one MTJ, aiming at a small cell area (up to 4 F2) equivalent to that of a flash memory (for example, refer to Patent Document 2). Furthermore, there is also a proposal whereby, in an element provided with a drive layer whose magnetization direction is essentially fixed in the stacking direction, transistors are reduced from two kinds to one kind, thus achieving a simplification of the circuit, by arranging in such away that the polarity of the current is in one direction only, and owing to the circuit configuration of one transistor to one MTJ obtained thereby, a cell size equivalent to the cell size of a DRAM is realized (for example, refer to Patent Document 3).